1. Field of the Invention
This invention concerns a semiconductor memory device. More particularly, this invention concerns an improvement of a sense amplifier circuit used in a semiconductor memory device.
2. Description of the Prior Art
The following items are important factors for a sense amplifier circuit used in a semiconductor memory device, e.g., a Static Random Access Memory (SRAM) device. (1) to output differential output signals of large amplitude with high sensitivity; (2) to have a wide sensing area or a large sensing margin against the variation of the bit line initial potential (bit line potential before the access to a memory cell) (3) a small occupying area and a low power consumption. FIG. 1 shows a conventional sense amplifier circuit used in a SRAM device. The sense amplifier 50 includes two sense amplifier circuits 51 and 52 each having a current mirror circuit 53 as a load circuit. The sense amplifier circuit 50 is superior in the above items (1) and (2), but is inferior in the above item (3) due to the use of two amplifier circuits 51 and 52.
Considering this point, an improved sense amplifier as shown in FIG. 2 is disclosed in Japanese laid open Patent: Hei 1-130619 (Japanese Patent Application: Sho 62-289773). As shown in FIG. 2, the sense amplifier circuit 60 includes a differential type sense amplifier circuit 61 and a bias circuit 62.
The differential type sense amplifier circuit 61 includes two P-type MOS (hereafter called as PMOS) transistors P1 and P2 and two N-type MOS (hereafter called as NMOS) transistors N3 and N4. The source electrodes of the transistors P1 and P2 are supplied with the power source voltage Vcc. The drain electrodes of the NMOS transistors N3 and N4 are connected to the drain electrodes of the transistors P1 and P2, and the source electrodes thereof are supplied with the reference voltage Vss through an NMOS transistor N5. The gate electrodes of the transistors N3 and N4 are connected to bit lines BL and BL, respectively.
The bias circuit 62 includes a PMOS transistor P6 and two NMOS transistor N7 and N8. The source electrode of the transistor P6 is supplied with the power source voltage Vcc, and the drain electrode and the gate electrode thereof are connected in common. The drain electrode of the transistor N7 is connected to the drain electrode of the transistor P6. The drain electrode of the transistor N8 is connected to the source electrode of the transistor N7, and the source electrode thereof is supplied with the reference voltage Vss.
The gate electrode of the transistor N7 is supplied with a constant voltage VC which is determined by the bit line initial potential. The gate electrode of the transistor N8 is supplied with the power source voltage Vcc. The gate electrodes of the transistors P1 and P2 are connected to the gate electrode of the transistor P6.
In this sense amplifier circuit, the impedance of the load circuit 63 composed of PMOS transistors P1 and P2 can be controlled so as to achieve a high sensitivity by adjusting the bias voltage VL. Since the bias voltage VL is adjustable by the constant voltage VC, the constant voltage VC is determined or set so as to achieve a high sensitivity considering the bit line initial potential. The constant voltage VC is equal to the bit line initial potential, for example.
However, the bit line potential varies between the bit lines due to the fluctuation of processing and the noise on the power source line. Therefore, it is difficult to represent the initial potential of the all bit lines by the single potential VC.
FIG. 3 shows a change of the sensitivity of the sense amplifier 61 with respect to the change of the bit line initial potential. In FIG. 3, it is assumed that 0.2 volt exists as a difference voltage between the bit lines in a pair, and a constant voltage VC of 2.0 volt is applied to the gate electrode of the NMOS transistor N7. As shown in FIG. 3, the sensing area where a high gain can be achieved is narrow. Thus, the choice of the constant voltage VC becomes critical.
To stabilize the bit line initial potential, a load circuit 80 is often used to set the bit line potential to Vcc-Vthn as shown in FIG. 4. Namely, the load circuit 80 includes NMOS transistors NL1 and NL2 which are supplied with an inverted signal W of the write control signal W at the gate electrodes thereof. By making the transistors NL1 and NL2 ON state, the initial bit line potential is set to Vcc-Vthn at the read operation. Vthn is the threshold voltage of the NMOS transistors NL1 and NL2.
However, when the SRAM cell 81 is not accessed for a relatively long time, the bit lines BL, BL are charged to approximately Vcc (overprecharge) by the leak current of the load transistors NL1 and NL2. Thus, the sensitivity of the sense amplifier circuit drops.